1. Field of the Invention
The invention relates to a semiconductor device, and more particularly, to a method for fabricating a non-volatile memory device.
2. Brief Description of Related Technology
A non-volatile memory device is electrically programmable and erasable, and has been widely used for electronic components where data is retained even when power is interrupted. A typical unit cell of the non-volatile memory device includes a floating gate and a control gate, and writes and erases data depending on whether electric charges are included in the floating gate.
In a floating gate type non-volatile memory device, it is important to form the floating gate to a small width because a sufficient distance should be obtained between adjacent floating gates in order to form the control gate. In particular, as high integration of a semiconductor device decreases the design rule, the pattern size is reduced. Therefore, it is difficult to form the control gate unless a sufficient distance is obtained between the floating gates. The floating gate and a semiconductor substrate are simultaneously etched for alignment of the floating gate.
FIG. 1 illustrates a cross-sectional view of a conventional non-volatile memory device.
Referring to FIG. 1, the conventional non-volatile memory device includes a tunneling layer 110, a floating gate 115, a dielectric layer 120, and a control gate 125 that are stacked on a semiconductor substrate 100. An isolation layer 105 defines an active region in the semiconductor substrate 100. An impurity region (not shown) such as source/drain regions is formed in the semiconductor substrate 100, and a channel region (not shown) is disposed between the source/drain regions. The isolation layer 105 is formed by etching the semiconductor substrate 100 to form a trench (during a process for patterning the floating gate 115), and filling the trench with a insulating layer.
When the floating gate 115 and the semiconductor substrate 100 are patterned together by etching, a width a1 of the floating gate 115 is equal to a width b1 of a portion of the semiconductor substrate 100 where the floating gate 115 is formed. As described above, a gap c1 between adjacent floating gates 115 should be obtained in order to form the control gate 125. However, it is difficult to form the floating gate 115 so as to have the width a1 different from the width b1 of the semiconductor substrate 100 during a process of etching the floating gate 115 and the semiconductor substrate 100 together. As a result, the floating gate 115 may be formed so as to have a slope. However, it is difficult to ensure the floating gate 115 has sufficient height when a line width is very small. In addition, if the width b1 of the semiconductor substrate 100 is small, a width of the channel region (not shown) is also reduced, thereby decreasing an operating current of a device. Therefore, it is necessary to obtain the gap c1 between the adjacent floating gates 115 while obtaining the sufficient width b1 of the semiconductor substrate 100 under the floating gate 115. Furthermore, a method of precisely controlling the height of the floating gate 115 is required.